Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 103
APB2 Clock Source Select
00: LOSC
01: OSC24M
1X: PLL_PERIPH0
This clock is used for some special module apbclk(UART、TWI). Because
these modules need special clock rate even if the apb1clk changed.
23:18
/
/
/
17:16
R/W
0x0
CLK_RAT_N
Clock Pre Divide Ratio (n)
The select clock source is pre-divided by 2^n. The divider is 1/2/4/8.
15:5
/
/
/
4:0
R/W
0x0
CLK_RAT_M.
Clock Divide Ratio (m)
The Pre Divide clock is divided by (m+1). The divider M is from 1 to 32.
4.3.5.13. AHB2 Configuration Register (Default Value: 0x00000000)
Offset: 0x005C
Register Name: AHB2_CFG_REG
Bit
R/W
Default/Hex
Description
31:2
/
/
/
1:0
R/W
0x0
AHB2_CLK_CFG.
00: AHB1 Clock
01: PLL_PERIPH0 / 2
1X: /
EMAC ,USBHCI1/2/3 default clock source is AHB2 Clock.
4.3.5.14. Bus Clock Gating Register0 (Default Value: 0x00000000)
Offset: 0x0060
Register Name: BUS_CLK_GATING_REG0
Bit
R/W
Default/Hex
Description
31
R/W
0x0
USBOHCI3_GATING.
Gating Clock for USB OHCI3
0: Mask
1: Pass
30
R/W
0x0
USBOHCI2_GATING.
Gating Clock for USB OHCI2
0: Mask
1: Pass
29
R/W
0x0
USBOHCI1_GATING.
Gating Clock for USB OHCI1
0: Mask
1: Pass
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