Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 105
16:15
/
/
/
14
R/W
0x0
DRAM_GATING.
Gating Clock For DRAM
0: Mask
1: Pass
13
R/W
0x0
NAND_GATING.
Gating Clock For NAND
0: Mask
1: Pass
12:11
/
/
/
10
R/W
0x0
MMC2_GATING.
Gating Clock For MMC2
0: Mask
1: Pass
9
R/W
0x0
MMC1_GATING.
Gating Clock For MMC1
0: Mask
1: Pass
8
R/W
0x0
MMC0_GATING.
Gating Clock For MMC0
0: Mask
1: Pass
7
/
/
/
6
R/W
0x0
DMA_GATING.
Gating Clock For DMA
0: Mask
1: Pass
5
R/W
0x0
CE_GATING.
Gating Clock For CE.
0: Mask
1: Pass
4:0
/
/
/
4.3.5.15. Bus Clock Gating Register1 (Default Value: 0x00000000)
Offset: 0x0064
Register Name: BUS_CLK_GATING_REG1
Bit
R/W
Default/Hex
Description
31:23
/
/
/
22
R/W
0x0
SPINLOCK_GATING.
0: Mask
1: Pass.
21
R/W
0x0
MSGBOX_GATING.
0: Mask
1: Pass.
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