Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 106
20
R/W
0x0
GPU_GATING.
0: Mask
1: Pass.
19:13
/
/
/
12
R/W
0x0
DE_GATING.
0: Mask
1: Pass.
11
R/W
0x0
HDMI_GATING.
0: Mask
1: Pass.
10
/
/
/
9
R/W
0x0
TVE_GATING.
Gating Clock For TVE
0: Mask
1: Pass.
8
R/W
0x0
CSI_GATING.
0: Mask
1: Pass.
7:6
/
/
/
5
R/W
0x0
DEINTERLACE_GATING.
Gating Clock For DEINTERLACE
0: Mask
1: Pass
4
R/W
0x0
TCON1_GATING.
Gating Clock For TCON1
0: Mask
1: Pass.
3
R/W
0x0
TCON0_GATING.
Gating Clock For TCON0
0: Mask
1: Pass.
2:1
/
/
/
0
R/W
0x0
VE_GATING.
Gating Clock For VE
0: Mask
1: Pass.
4.3.5.16. Bus Clock Gating Register2 (Default Value: 0x00000000)
Offset: 0x0068
Register Name: BUS_CLK_GATING_REG2
Bit
R/W
Default/Hex
Description
31:15
/
/
/
14
R/W
0x0
I2S/PCM 2_GATING.
Gating Clock For I2S/PCM 2
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