Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 108
Gating Clock For UART2
0: Mask
1: Pass.
17
R/W
0x0
UART1_GATING.
Gating Clock For UART1
0: Mask
1: Pass.
16
R/W
0x0
UART0_GATING.
Gating Clock For UART0
0: Mask
1: Pass.
15:3
/
/
/
2
R/W
0x0
TWI2_GATING.
Gating Clock For TWI2
0: Mask
1: Pass.
1
R/W
0x0
TWI1_GATING.
Gating Clock For TWI1
0: Mask
1: Pass.
0
R/W
0x0
TWI0_GATING.
Gating Clock For TWI0
0: Mask
1: Pass.
4.3.5.18. Bus Clock Gating Register4 (Default Value: 0x00000000)
Offset: 0x0070
Register Name: BUS_CLK_GATING_REG4
Bit
R/W
Default/Hex
Description
31:8
/
/
/
7
R/W
0x0
DBGSYS_GATING.
Gating Clock For DBGSYS
0: Mask
1: Pass
6:1
/
/
/
0
R/W
0x0
EPHY_GATING.
Gating Clock For EPHY
0: Mask
1: Pass
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