Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 109
4.3.5.19. THS Clock Register (Default Value: 0x00000000)
Offset: 0x0074
Register Name: THS_CLK_REG
Bit
R/W
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock.
0: Clock is OFF
1: Clock is ON
This special clock = Clock Source/CLK_DIV_RATIO.
30:26
/
/
/
25:24
R/W
0x0
THS_CLK_SRC_SEL.
Clock Source Select
00: OSC24M
01: /
10: /
11: /
23:2
/
/
/
1:0
R/W
0x0
THS_CLK_DIV_RATIO.
THS clock divide ratio.
00: /1
01: /2
10: /4
11: /6
4.3.5.20. NAND Clock Register (Default Value: 0x00000000)
Offset: 0x0080
Register Name: NAND_CLK_REG
Bit
R/W
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock(Max Clock = 200MHz)
0: Clock is OFF
1: Clock is ON.
SCLK = Clock Source/Divider N/Divider M.
30:26
/
/
/
25:24
R/W
0x0
CLK_SRC_SEL.
Clock Source Select
00: OSC24M
01: PLL_PERIPH0
10: PLL_PERIPH1
11: /
23:18
/
/
/
17:16
R/W
0x0
CLK_DIV_RATIO_N.
Clock Pre Divide Ratio (n)
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