Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 110
00: /1
01: /2
10: /4
11: /8 .
15:4
/
/
/
3:0
R/W
0x0
CLK_DIV_RATIO_M
Clock Divide Ratio (m)
The pre-divided clock is divided by (m+1). The divider M is from 1 to 16.
4.3.5.21. SDMMC0 Clock Register (Default Value: 0x00000000)
Offset: 0x0088
Register Name: SDMMC0_CLK_REG
Bit
R/W
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock(Max Clock = 200MHz)
0: Clock is OFF
1: Clock is ON.
SCLK = Clock Source/Divider N/Divider M.
30:26
/
/
/
25:24
R/W
0x0
CLK_SRC_SEL.
Clock Source Select
00: OSC24M
01: PLL_PERIPH0
10: PLL_PERIPH1
11: /
23
/
/
/
22:20
R/W
0x0
SAMPLE_CLK_PHASE_CTR.
Sample Clock Phase Control.
The sample clock phase delay is based on the number of source clock that is
from 0 to 7.
19:18
/
/
/
17:16
R/W
0x0
CLK_DIV_RATIO_N.
Clock Pre Divide Ratio (n)
00: /1
01: /2
10: /4
11: /8 .
15:11
/
/
/
10:8
R/W
0x0
OUTPUT_CLK_PHASE_CTR.
Output Clock Phase Control.
The output clock phase delay is based on the number of source clock that is
from 0 to 7.
7:4
/
/
/
3:0
R/W
0x0
CLK_DIV_RATIO_M.
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