Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 113
4.3.5.24. TS Clock Register (Default Value: 0x00000000)
Offset: 0x0098
Register Name: TS_CLK_REG
Bit
R/W
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock(Max Clock = 200MHz)
0: Clock is OFF
1: Clock is ON.
SCLK = Clock Source/Divider N/Divider M.
30:28
/
/
/
27:24
R/W
0x0
CLK_SRC_SEL.
Clock Source Select
0000: OSC24M
0001: PLL_PERIPH0
Others: /
23:18
/
/
/
17:16
R/W
0x0
CLK_DIV_RATIO_N.
Clock pre-divide ratio (n)
The select clock source is pre-divided by 2^n. The divider is 1/2/4/8.
15:4
/
/
/
3:0
R/W
0x0
CLK_DIV_RATIO_M.
Clock divide ratio (m)
The pre-divided clock is divided by (m+1). The divider is from 1 to 16.
4.3.5.25. CE Clock Register (Default Value: 0x00000000)
Offset: 0x009C
Register Name: CE_CLK_REG
Bit
R/W
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock(Max Clock = 400MHz)
0: Clock is OFF
1: Clock is ON.
SCLK = Clock Source/Divider N/Divider M.
30:26
/
/
/
25:24
R/W
0x0
CLK_SRC_SEL.
Clock Source Select
00: OSC24M
01: PLL_PERIPH0
10: PLL_PERIPH1
11: /
23:18
/
/
/
17:16
R/W
0x0
CLK_DIV_RATIO_N.
Clock Pre Divide Ratio (n)
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