Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 116
4.3.5.29. I2S/PCM 1 Clock Register (Default Value: 0x00000000)
Offset: 0x00B4
Register Name: I2S/PCM 1_CLK_REG
Bit
R/W
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock(Max Clock = 200MHz)
0: Clock is OFF
1: Clock is ON.
30:18
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17:16
R/W
0x0
CLK_SRC_SEL.
00: PLL_AUDIO (8X)
01: PLL_AUDIO(8X)/2
10: PLL_AUDIO(8X)/4
11: PLL_AUDIO
15:0
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4.3.5.30. I2S/PCM 2 Clock Register (Default Value: 0x00000000)
Offset: 0x00B8
Register Name: I2S/PCM 2_CLK_REG
Bit
R/W
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock(Max Clock = 200MHz)
0: Clock is OFF
1: Clock is ON.
30:18
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17:16
R/W
0x0
CLK_SRC_SEL.
00: PLL_AUDIO (8X)
01: PLL_AUDIO(8X)/2
10: PLL_AUDIO(8X)/4
11: PLL_AUDIO
15:0
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4.3.5.31. OWA Clock Register (Default Value: 0x00000000)
Offset: 0x00C0
Register Name: OWA_CLK_REG
Bit
R/W
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock(Max Clock = 200MHz)
0: Clock is OFF
1: Clock is ON.
SCLK= PLL_AUDIO/Divider M.
30:4
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