Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 117
3:0
R/W
0x0
CLK_DIV_RATIO_M.
Clock Divide Ratio (m)
The pre-divided clock is divided by (m+1). The divider M is from 1 to 16.
4.3.5.32. USBPHY Configuration Register (Default Value: 0x00000000)
Offset: 0x00CC
Register Name: USBPHY_CFG_REG
Bit
R/W
Default/Hex
Description
31:20
/
/
/
19
R/W
0x0
SCLK_GATING_OHCI3.
Gating Special Clock For OHCI3
0: Clock is OFF
1: Clock is ON
18
R/W
0x0
SCLK_GATING_OHCI2.
Gating Special Clock For OHCI2
0: Clock is OFF
1: Clock is ON
17
R/W
0x0
SCLK_GATING_OHCI1.
Gating Special Clock For OHCI1
0: Clock is OFF
1: Clock is ON
16
R/W
0x0
SCLK_GATING_OTG_OHCI0.
Gating Special Clock For USB OTG_OHCI0
0: Clock is OFF
1: Clock is ON
15:12
/
/
/
11
R/W
0x0
SCLK_GATING_USBPHY3.
Gating Special Clock For USB PHY3
0: Clock is OFF
1: Clock is ON
10
R/W
0x0
SCLK_GATING_USBPHY2.
Gating Special Clock For USB PHY2
0: Clock is OFF
1: Clock is ON
9
R/W
0x0
SCLK_GATING_USBPHY1.
Gating Special Clock For USB PHY1
0: Clock is OFF
1: Clock is ON
8
R/W
0x0
SCLK_GATING_USBPHY0.
Gating Special Clock For USB PHY0
0: Clock is OFF
1: Clock is ON
7:4
/
/
/
3
R/W
0x0
USBPHY3_RST.
confidential