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System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 118
USB PHY3 Reset Control
0: Assert
1: De-assert
2
R/W
0x0
USBPHY2_RST.
USB PHY2 Reset Control
0: Assert
1: De-assert.
1
R/W
0x0
USBPHY1_RST.
USB PHY1 Reset Control
0: Assert
1: De-assert
0
R/W
0x0
USBPHY0_RST.
USB PHY0 Reset Control
0: Assert
1: De-assert
4.3.5.33. DRAM Configuration Register (Default Value: 0x00000000)
Offset: 0x00F4
Register Name: DRAM_CFG_REG
Bit
R/W
Default/Hex
Description
31
R/W
0x0
DRAM_CTR_RST.
DRAM Controller Reset For AHB Clock Domain.
0: Assert
1: De-assert.
30:22
21:20
R/W
0x0
CLK_SRC_SEL.
00: PLL_DDR
01: PLL_PERIPH0 (2X)
Others: /
19:17
/
/
/
16
R/W
0x0
SDRCLK_UPD.
SDRCLK Configuration Update.
0:Invalid
1:Valid.
Note: Set this bit will validate Configuration . It will be auto cleared after the
Configuration is valid.
The DRAMCLK Source is from PLL_DDR.
15:4
/
/
/
3:0
R/W
0x0
DRAM_DIV_M.
DRAMCLK Divider of Configuration.
The clock is divided by (m+1). The divider M should be from 1 to 16.
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