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System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 119
4.3.5.34. MBUS Reset Register (Default Value: 0x80000000)
Offset: 0x00FC
Register Name: MBUS_RST_REG
Bit
R/W
Default/Hex
Description
31
R/W
0x1
MBUS_RESET.
0: Reset Mbus Domain
1: Assert Mbus Domain.
30:0
/
/
/
4.3.5.35. DRAM Clock Gating Register (Default Value: 0x00000000)
Offset: 0x0100
Register Name: DRAM_CLK_GATING_REG
Bit
R/W
Default/Hex
Description
31:4
/
/
/
3
R/W
0x0
TS_DCLK_GATING.
Gating DRAM Clock For TS
0: Mask
1: Pass
2
R/W
0x0
DEINTERLACE_DCLK_GATING.
Gating DRAM SCLK(1X) For DEINTERLACE
0: Mask
1: Pass
1
R/W
0x0
CSI_DCLK_GATING.
Gating DRAM Clock For CSI
0: Mask
1: Pass
0
R/W
0x0
VE_DCLK_GATING.
Gating DRAM Clock For VE
0: Mask
1: Pass
4.3.5.36. DE Clock Gating Register (Default Value: 0x00000000)
Offset: 0x0104
Register Name: DE_CLK_REG
Bit
R/W
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock
0: Clock is OFF
1: Clock is ON
This special clock = Clock Source/Divider M.
30:27
/
/
/
26:24
R/W
0x0
CLK_SRC_SEL.
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