Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 120
Clock Source Select
000: PLL_PERIPH0(2X)
001: PLL_DE
Others: /
23:4
/
/
/
3:0
R/W
0x0
CLK_DIV_RATIO_M.
Clock Divide Ratio (m)
The pre-divided clock is divided by (m+1). The divider is from 1 to 16.
4.3.5.37. TCON0 Clock Register (Default Value: 0x00000000)
Offset: 0x0118
Register Name: TCON0_CLK_REG
Bit
R/W
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock
0: Clock is OFF
1: Clock is ON.
30:27
/
/
/
26:24
R/W
0x0
CLK_SRC_SEL.
Clock Source Select
000: PLL_VIDEO
Others: /.
23:4
/
/
/
3:0
R/W
0x0
CLK_DIV_RATIO_M.
Clock Divide Ratio (m)
The pre-divided clock is divided by (m+1). The divider M is from 1 to 16.
4.3.5.38. TVE Clock Register (Default Value: 0x00000000)
Offset: 0x0120
Register Name: TVE_CLK_REG
Bit
R/W
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock
0: Clock is OFF
1: Clock is ON
SCLK= Clock Source/ Divider M.
30:27
/
/
/
26:24
R/W
0x0
CLK_SRC_SEL.
Clock Source Select
000: PLL_DE
001: PLL_PERIPH1
Others: /
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