Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 122
0: Clock is OFF
1: Clock is ON.
SCLK= Special Clock Source/CSI_SCLK_DIV_M.
30:27
/
/
/
26:24
R/W
0x0
SCLK_SRC_SEL.
Special Clock Source Select
000: PLL_PERIPH0
001: PLL_PERIPH1
Others: /
23:20
/
/
/
19:16
R/W
0x0
CSI_SCLK_DIV_M.
CSI Clock Divide Ratio (m)
The pre-divided clock is divided by (m+1). The divider M is from 1 to 16.
15
R/W
0x0
CSI_MCLK_GATING.
Gating Master Clock
0: Clock is OFF
1: Clock is ON
This clock =Master Clock Source/ CSI_MCLK_DIV_M.
14:11
/
/
/
10:8
R/W
0x0
MCLK_SRC_SEL.
Master Clock Source Select
000: OSC24M
001: PLL_VIDEO
010: PLL_PERIPH1
Others: /
7:5
/
/
/
4:0
R/W
0x0
CSI_MCLK_DIV_M.
CSI Master Clock Divide Ratio (m)
The pre-divided clock is divided by (m+1). The divider is from 1 to 32.
4.3.5.42. VE Clock Register (Default Value: 0x00000000)
Offset: 0x013C
Register Name: VE_CLK_REG
Bit
R/W
Default/Hex
Description
31
R/W
0x0
VE_SCLK_GATING.
Gating Special Clock
0: Clock is OFF
1: Clock is ON.
SCLK = PLL_VE /Divider N.
30:19
/
/
/.
18:16
R/W
0x0
CLK_DIV_RATIO_N.
Clock Pre Divide Ratio (N)
The select clock source is pre-divided by n+1. The divider N is from 1 to 8.
15:0
/
/
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