Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 123
4.3.5.43. AC Digital Clock Register (Default Value: 0x00000000)
Offset: 0x0140
Register Name: AC_DIG_CLK_REG
Bit
R/W
Default/Hex
Description
31
R/W
0x0
SCLK_1X_GATING.
Gating Special Clock
0: Clock is OFF
1: Clock is ON
SCLK = PLL_AUDIO Output.
30:0
/
/
/
4.3.5.44. AVS Clock Register (Default Value: 0x00000000)
Offset: 0x0144
Register Name: AVS_CLK_REG
Bit
R/W
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock
0: Clock is OFF
1: Clock is ON.
SCLK= OSC24M.
30:0
/
/
/
4.3.5.45. HDMI Clock Register (Default Value: 0x00000000)
Offset: 0x0150
Register Name: HDMI_CLK_REG
Bit
R/W
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock
0: Clock is OFF
1: Clock is ON.
SCLK= Clock Source/ Divider M.
30:26
/
/
/
25:24
R/W
0x0
SCLK_SEL.
Special Clock Source Select
00: PLL_VIDEO
Others: /
23:4
/
/
/
3:0
R/W
0x0
CLK_DIV_RATIO_M.
Clock Divide Ratio (m)
The pre-divided clock is divided by (m+1). The divider M is from 1 to 16.
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