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System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 124
4.3.5.46. HDMI Slow Clock Register (Default Value: 0x00000000)
Offset: 0x0154
Register Name: HDMI_SLOW_CLK_REG
Bit
R/W
Default/Hex
Description
31
R/W
0x0
HDMI_DDC_CLK_GATING.
0: Clock is OFF
1: Clock is ON.
SCLK = OSC24M.
30:0
/
/
/
4.3.5.47. MBUS Clock Register (Default Value: 0x00000000)
Offset: 0x015C
Register Name: MBUS_CLK_REG
Bit
R/W
Default/Hex
Description
31
R/W
0x0
MBUS_SCLK_GATING.
Gating Clock for MBUS
0: Clock is OFF
1: Clock is ON.
MBUS_CLOCK = Clock Source/Divider M
30:26
/
/
/
25:24
R/W
0x0
MBUS_SCLK_SRC
Clock Source Select
00: OSC24M
01: PLL_PERIPH0(2X)
10: PLL_DDR
11: /.
23:3
/
/
/
2:0
R/W
0x0
MBUS_SCLK_RATIO_M
Clock Divide Ratio (m)
The pre-divided clock is divided by (m+1). The divider M is from 1 to 8.
Note: If the clock has been changed ,it must wait for at least 16 cycles.
4.3.5.48. GPU Clock Register (Default Value: 0x00000000)
Offset: 0x01A0
Register Name: GPU_CLK_REG
Bit
R/W
Default/Hex
Description
31
R/W
0x0
SCLK_GATING.
0: Clock is OFF
1: Clock is ON.
SCLK= PLL-GPU/Divider N.
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