Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 125
30:3
/
/
/.
2:0
R/W
0x0
CLK_DIV_RATIO_N.
Clock Pre Divide Ratio (N)
The select clock source is pre-divided by( n+1). The divider N is from 1 to 8.
4.3.5.49. PLL Stable Time Register0 (Default Value: 0x000000FF)
Offset: 0x0200
Register Name: PLL_STABLE_TIME_REG0
Bit
R/W
Default/Hex
Description
31:16
/
/
/
15:0
R/W
0x00FF
PLL_LOCK_TIME
PLL Lock Time (Unit: us).
Note: When any PLL (except PLL_CPU) is enabled or changed, the
corresponding PLL lock bit will be set after the PLL STABLE Time.
4.3.5.50. PLL Stable Time Register1 (Default Value: 0x000000FF)
Offset: 0x0204
Register Name: PLL_STABLE_TIME_REG1
Bit
R/W
Default/Hex
Description
31:16
/
/
/
15:0
R/W
0x00FF
PLL_CPU_LOCK_TIME
PLL_CPU Lock Time (Unit: us).
Note: When PLL_CPU is enabled or changed, the PLL_CPU lock bit will be set
after the PLL_CPU STABLE Time.
4.3.5.51. PLL_CPUX Bias Register (Default Value: 0x08100200)
Offset: 0x0220
Register Name: PLL_CPUX_BIAS_REG
Bit
R/W
Default/Hex
Description
31
R/W
0x0
VCO_RST.
VCO reset in.
30:29
/
/
/
28
R/W
0x0
EXG_MODE.
Exchange Mode.
Note: CPU PLL source will select PLL_PERIPH0 instead of PLL_CPU
27:24
R/W
0x8
PLL_VCO_BIAS_CTRL.
PLL VCO Bias Control[3:0].
23:21
/
/
/
20:16
R/W
0x10
PLL_BIAS_CUR_CTRL.
PLL Bias Current Control[4:0].
15:11
/
/
/
confidential