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System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 127
20:16
R/W
0x10
PLL_BIAS_CTRL.
PLL Bias Control[4:0].
15:3
/
/
/
2:0
R/W
0x0
PLL_DAMP_FACTOR_CTRL.
PLL Damping Factor Control[2:0].
4.3.5.55. PLL_DDR Bias Register (Default Value: 0x81104000)
Offset: 0x0230
Register Name: PLL_DDR_BIAS_REG
Bit
R/W
Default/Hex
Description
31:28
R/W
0x8
PLL_VCO_BIAS.
PLL VCO Bias[3:0].
27:26
/
/
/.
25
R/W
0x0
PLL_VCO_GAIN_CTRL_EN.
PLL VCO Gain Control Enable.
0: Disable
1: Enable.
24
R/W
0x1
PLL_BANDW_CTRL.
PLL Band Width Control.
0: Narrow
1: Wide.
23:21
/
/
/
20:16
R/W
0x10
PLL_BIAS_CUR_CTRL.
PLL Bias Current Control.
15
/
/
/
14:12
R/W
0x4
PLL_VCO_GAIN_CTRL.
PLL VCO Gain Control Bit[2:0].
11:4
/
/
/
3:0
R/W
0x0
PLL_DAMP_FACTOR_CTRL.
PLL Damping Factor Control[3:0].
4.3.5.56. PLL_PERIPH0 Bias Register (Default Value: 0x10100010)
Offset: 0x0234
Register Name: PLL_PERIPH0_BIAS_REG
Bit
R/W
Default/Hex
Description
31:29
/
/
/
28:24
R/W
0x10
PLL_VCO_BIAS.
PLL VCO Bias[4:0].
23:21
/
/
/
20:16
R/W
0x10
PLL_BIAS_CUR_CTRL.
PLL Bias Current Control.
15:5
/
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