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System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 129
4.3.5.59. PLL_DE Bias Register (Default Value: 0x10100000)
Offset: 0x0248
Register Name: PLL_DE_BIAS_REG
Bit
R/W
Default/Hex
Description
31:29
/
/
/
28:24
R/W
0x10
PLL_VCO_BIAS_CTRL.
PLL VCO Bias Control[4:0].
23:21
/
/
/
20:16
R/W
0x10
PLL_BIAS_CTRL.
PLL Bias Control[4:0].
15:3
/
/
/
2:0
R/W
0x0
PLL_DAMP_FACTOR_CTRL.
PLL Damping Factor Control[2:0].
4.3.5.60. PLL_CPUX Tuning Register (Default Value: 0x0A101000)
Offset: 0x0250
Register Name: PLL_CPUX_TUN_REG
Bit
R/W
Default/Hex
Description
31:28
/
/
/
27
R/W
0x1
PLL_BAND_WID_CTRL.
PLL Band Width Control.
0: Narrow
1: Wide
26
R/W
0x0
VCO_GAIN_CTRL_EN.
VCO Gain Control Enable.
0: Disable
1: Enable
25:23
R/W
0x4
VCO_GAIN_CTRL.
VCO Gain Control Bits[2:0].
22:16
R/W
0x10
PLL_INIT_FREQ_CTRL.
PLL Initial Frequency Control[6:0].
15
R/W
0x0
C_OD.
C-Reg-Od For Verify.
14:8
R/W
0x10
C_B_IN.
C-B-In[6:0] For Verify.
7
R/W
0x0
C_OD1.
C-Reg-Od1 For Verify.
6:0
R
0x0
C_B_OUT.
C-B-Out[6:0] For Verify.
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