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System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 130
4.3.5.61. PLL_DDR Tuning Register (Default Value: 0x14880000)
Offset: 0x0260
Register Name: PLL_DDR_TUN_REG
Bit
R/W
Default/Hex
Description
31:29
/
/
/
28
R/W
0x1
VREG1_OUT_EN.
Vreg1 Out Enable.
0: Disable
1: Enable
27
/
/
/
26:24
R/W
0x4
PLL_LTIME_CTRL.
PLL Lock Time Control[2:0].
23
R/W
0x0
VCO_RST.
VCO Reset In.
22:16
R/W
0x10
PLL_INIT_FREQ_CTRL.
PLL Initial Frequency Control[6:0].
15
R/W
0x0
OD1.
Reg-Od1 For Verify.
14:8
R/W
0x10
B_IN.
B-In[6:0] For Verify.
7
R/W
0x0
OD.
Reg-Od For Verify.
6:0
R
0x0
B_OUT.
B-Out[6:0] For Verify.
4.3.5.62. PLL_CPUX Pattern Control Register (Default Value: 0x00000000)
Offset: 0x0280
Register Name: PLL_CPUX_PAT_CTRL_REG
Bit
R/W
Default/Hex
Description
31
R/W
0x0
SIG_DELT_PAT_EN.
Sigma-delta Pattern Enable.
30:29
R/W
0x0
SPR_FREQ_MODE.
Spread Frequency Mode.
00: DC=0
01: DC=1
1X: Triangular
28:20
R/W
0x0
WAVE_STEP.
Wave Step.
19
/
/
/
18:17
R/W
0x0
FREQ.
Frequency.
00: 31.5KHz
01: 32KHz
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