Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 136
1: De-assert
19
R/W
0x0
HSTMR_RST.
HSTMR Reset.
0: Assert
1: De-assert
18
R/W
0x0
TS_RST.
TS Reset.
0: Assert
1: De-assert
17
R/W
0x0
EMAC_RST.
EMAC Reset.
0: Assert
1: De-assert
16:15
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/
/
14
R/W
0x0
SDRAM_RST.
SDRAM AHB Reset.
0: Assert
1: De-assert
13
R/W
0x0
NAND_RST.
NAND Reset.
0: Assert
1: De-assert
12:11
/
/
/
10
R/W
0x0
SD2_RST.
SD/MMC2 Reset.
0: Assert
1: De-assert
9
R/W
0x0
SD1_RST.
SD/MMC1 Reset.
0: Assert
1: De-assert
8
R/W
0x0
SD0_RST.
SD/MMC0 Reset.
0: Assert
1: De-assert
7
/
/
/
6
R/W
0x0
DMA_RST.
DMA Reset.
0: Assert
1: De-assert
5
R/W
0x0
CE_RST.
CE Reset.
0: Assert
1: De-assert
4:0
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