Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 140
2
R/W
0x0
TWI2_RST.
TWI2 Reset.
0: Assert
1: De-assert.
1
R/W
0x0
TWI1_RST.
TWI1 Reset.
0: Assert
1: De-assert.
0
R/W
0x0
TWI0_RST.
TWI0 Reset.
0: Assert
1: De-assert.
4.3.5.75. CCU Security Switch Register (Default Value: 0x00000000)
Offset: 0x02F0
Register Name: CCU_SEC_SWITCH_REG
Bit
R/W
Default/Hex
Description
31:3
/
/
/
2
R/W
0x0
MBUS_SEC
MBUS clock register security
0:Secure
1:Non-secure
Including MBUS Reset Register and MBUS Clock Register
1
R/W
0x0
BUS_SEC
Bus relevant registers’ security
0:Secure
1:Non-secure
Including AXI/AHB/APB relevant registers,such as CPUX/AXI Configuration
Register,AHB1/APB1 Configuration Register,APB2 Configuration Register,
AHB2 Configuration Register.
0
R/W
0x0
PLL_SEC
PLL relevant registers’ security.
0:Secure
1:Non-secure
Including PLL_CPUX Control Register,PLL_AUDIO Control Register,PLL_VIDEO
Control Register,PLL_VE Control Register,PLL_DDR Control Register,PLL_
PEPIPH0 Control Register,PLL_GPU Control Register,PLL_PERIPH1 Control
Register,PLL_DE Control Register and offset from 0x200 to 0x2A8 relevant
registers.
4.3.5.76. PS Control Register (Default Value: 0x00000000)
Offset: 0x0300
Register Name: PS_CTRL_REG
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