Owners manual

System

4.3.6. Programming Guidelines

4.3.6.1. PLL

1) In practical application, other PLLs doesn’t support dynamic frequency scaling except for PLL_CPUX;

2) After the PLL_DDR frequency changes, the 20-bit of PLL_DDR Control Register should be written 1 to make it valid;

4.3.6.2. BUS

1) When setting the BUS clock , you should set the division factor first, and after the division factor becomes valid,

switch the clock source. The clock source will be switched after at least three clock cycles;

2) The BUS clock should not be dynamically changed in most applications.

4.3.6.3. Clock Switch

Make sure that the clock source output is valid before the clock source switch, and then set a proper divide ratio; after

the division factor becomes valid, switch the clock source.

4.3.6.4. Gating and reset

Make sure that the reset signal has been released before the release of module clock gating;

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