Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 144
4.4.3. Register Description
4.4.3.1. CPUS Reset Control Register(Default Value: 0x00000000)
Offset: 0x00
Register Name: CPUS_RST_CTRL_REG
Bit
R/W
Default/Hex
Description
31:1
/
/
/
0
R/W
0x0
CPUS_RESET.
CPUS Reset Assert.
0: assert
1: de-assert.
4.4.3.2. CPU0 Reset Control Register(Default Value: 0x00000000)
Offset: 0x40
Register Name: CPU0_RST_CTRL_REG
Bit
R/W
Default/Hex
Description
31:2
/
/
/
1
R/W
0x1
CPU0_CORE_REST.
These are the primary reset signals which initialize the processor logic in the
processor power domains, not including the debug, breakpoint and
watchpoint logic.
0: assert
1: de-assert.
0
R/W
0x1
CPU0_RESET.
CPU0 Power-on Reset Assert.
These power-on reset signals initialize all the processor logic, including CPU
Debug, and breakpoint and watch point logic in the processor power
domains. They do not reset debug logic in the debug power domain.
0: assert
1: de-assert.
4.4.3.3. CPU0 Control Register(Default Value: 0x00000000)
Offset: 0x44
Register Name: CPU0_CTRL_REG
Bit
R/W
Default/Hex
Description
31:1
/
/
/
0
R/W
0x0
CPU0_CP15_WRITE_DISABLE.
Disable write access to certain CP15 registers.
0: enable
1: disable
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