Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 146
Disable write access to certain CP15 registers.
0: enable
1: disable
4.4.3.7. CPU1 Status Register(Default Value: 0x00000000)
Offset: 0x88
Register Name: CPU1_STATUS_REG
Bit
R/W
Default/Hex
Description
31:3
/
/
/.
2
R
0x0
STANDBYWFI.
Indicates if the processor is in WFI standby mode:
0: Processor not in WFI standby mode.
1: Processor in WFI standby mode
1
R
0x0
STANDBYWFE.
Indicates if the processor is in the WFE standby mode:
0: Processor not in WFE standby mode
1: Processor in WFE standby mode
0
R
0x0
SMP_AMP
0: AMP mode
1: SMP mode
4.4.3.8. CPU2 Reset Control Register(Default Value: 0x00000001)
Offset: 0xC0
Register Name: CPU2_RST_CTRL_REG
Bit
R/W
Default/Hex
Description
31:2
/
/
/.
1
R/W
0x0
CPU2_CORE_REST.
These are the primary reset signals which initialize the processor logic in the
processor power domains, not including the debug, breakpoint and watch
point logic.
0: assert
1: de-assert.
0
R/W
0x1
CPU2_RESET.
CPU2 Reset Assert.
These power-on reset signals initialize all the processor logic, including CPU
Debug, and breakpoint and watch point logic in the processor power
domains. They do not reset debug logic in the debug power domain.
0: assert
1: de-assert.
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