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System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 148
domains. They do not reset debug logic in the debug power domain.
0: assert
1: de-assert.
4.4.3.12. CPU3 Control Register(Default Value: 0x00000000)
Offset: 0x104
Register Name: CPU3_CTRL_REG
Bit
R/W
Default/Hex
Description
31:1
/
/
/
0
R/W
0x0
CPU3_CP15_WRITE_DISABLE.
Disable write access to certain CP15 registers.
0: enable
1: disable
4.4.3.13. CPU3 Status Register(Default Value: 0x00000000)
Offset: 0x108
Register Name: CPU3_STATUS_REG
Bit
R/W
Default/Hex
Description
31:3
/
/
/.
2
R
0x0
STANDBYWFI.
Indicates if the processor is in WFI standby mode:
0: Processor not in WFI standby mode.
1: Processor in WFI standby mode
1
R
0x0
STANDBYWFE.
Indicates if the processor is in the WFE standby mode:
0: Processor not in WFE standby mode
1: Processor in WFE standby mode
0
R
0x0
SMP_AMP
0: AMP mode
1: SMP mode
4.4.3.14. CPU System Reset Control Register(Default Value: 0x00000001)
Offset: 0x140
Register Name: CPU_SYS_RST_REG
Bit
R/W
Default/Hex
Description
31:1
/
/
/
0
R/W
0x1
CPU System Reset Control.
0: assert
1: de-assert.
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