Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 149
4.4.3.15. CPU Clock Gating Register(Default Value: 0x0000010F)
Offset: 0x144
Register Name: CPU_CLK_GATING_REG
Bit
R/W
Default/Hex
Description
31:9
/
/
/
8
R/W
0x1
L2_CLK_GATING
L2 Clock gating
0: clock off
1: clock on
7:4
/
/
/
3:0
R/W
0xF
CPU_CLK_GATING
CPU0/1/2/3 Clock gating
0: clock off
1: clock on
4.4.3.16. General Control Register(Default Value: 0x00000020)
Offset: 0x184
Register Name: GENER_CTRL_REG
Bit
R/W
Default/Hex
Description
31:9
/
/
/.
8
R/W
0x0
CFGSDISABLE.
Disables write access to some secure GIC registers.
7
/
/
/
6
R/W
0x0
ACINACTM.
Snoop interface is inactive and no longer accepting requests.
5
R/W
0x1
L2_RST.
L2 Reset.(SCU global reset)
0: Apply reset to shared L2 memory system controller.
1: Do not apply reset to shared L2 memory system controller.
4
R/W
0x0
L2_RST_DISABLE.
Disable automatic L2 cache invalidate at reset:
0: L2 cache is reset by hardware.
1: L2 cache is not reset by hardware.
3:0
R/W
0x0
L1_RST_DISABLE.
L1 Reset Disable[3:0].
0: L1 cache is reset by hardware.
1: L1 cache is not reset by hardware.
4.4.3.17. Super Standby Flag Register(Default Value: 0x00000000)
Offset: 0x1A0
Register Name: SUP_STAN_FLAG_REG
Bit
R/W
Default/Hex
Description
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