Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 150
31:16
R/W
0x0
SUP_STANDBY_FLAG.
Key Field.
Any value can be written and read back in the key field, but if the values are
not appropriate, the lower 16 bits will not change in this register. Only fellow
the appropriate process, the super standby flag can be written in the lower
16 bits. Refer to Description and Diagram.
15:0
R/W
0x0
SUP_STANBY_FLAG_DATA.
Refer to Description and Diagram
Note: When system is turned on, the value in the Super Standby Flag Register low 16 bits should be 0x0. If software
programmer wants to write correct super standby flag ID in low 16 bits, the high 16 bits should be written 0x16AA at
first. Then, software programmer must write 0xAA16XXXX in the Super Standby Flag Register, the ‘XXXX’ means the
correct super standby flag ID. Referring to the Diagram section (Diagram 1.1) in detail.
4.4.3.18. 64-bit Counter Control Register(Default Value: 0x00000000)
Offset: 0x280
Register Name: CNT64_CTRL_REG
Bit
R/W
Default/Hex
Description
31:3
/
/
/.
2
R/W
0x0
CNT64_CLK_SRC_SEL.
64-bit Counter Clock Source Select.
0: OSC24M
1: /
1
R/W
0x0
CNT64_RL_EN.
64-bit Counter Read Latch Enable.
0: no effect, 1: to latch the 64-bit Counter to the Low/Hi registers and it will
change to zero after the registers are latched.
0
R/W
0x0
CNT64_CLR_EN.
64-bit Counter Clear Enable.
0: no effect, 1: to clear the 64-bit Counter Low/Hi registers and it will change
to zero after the registers are cleared.
Note: It is not recommended to clear this counter arbitrarily.
Note: This 64-bit counter will start to count as soon as the System Power On finished.
4.4.3.19. 64-bit Counter Low Register(Default Value: 0x00000000)
Offset: 0x284
Register Name: CNT64_LOW_REG
Bit
R/W
Default/Hex
Description
31:0
R/W
0x0
CNT64_LO.
64-bit Counter [31:0].
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