Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 152
4.5. System Control
4.5.1. Overview
Area
Size(Bytes)
A1
64K
A2
32K
CPUX I-Cache
32K (X=0,1,2,3)
CPUX D-Cache
32K (X=0,1,2,3)
CPU L2 Cache
512K
Total
864K
4.5.2. System Control Register List
Module Name
Base Address
System Control
0x01C00000
Register Name
Offset
Description
VER_REG
0x24
Version Register
EMAC_EPHY_CLK_REG
0x30
EMAC-EPHY Clock Register
4.5.3. System Control Register Description
4.5.3.1. Version Register
Offset:0x24
Register Name: VER_REG
Bit
R/W
Default/Hex
Description
31:9
/
/
/
8
R
x
UBOOT_SEL_PAD_STA.
U_boot Select Pin Status.
0: U_Boot;
1: Normal Boot.
7:0
R
0x0
VER_BITS.
This read-only bit field always reads back the mask revision level of the
chip.
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