Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 153
4.5.3.2. EMAC Clock Register (Default Value: 0x00058000)
Offset:0x30
Register Name: EMAC_CLK_REG
Bit
R/W
Default/Hex
Description
31:28
R/W
0x0
BPS_EFFUSE
27
R/W
0x0
XMII_SEL
0: Internal SMI and MII
1: External SMI and MII
26:25
R/W
0x0
EPHY_MODE
Operation Mode Selection
00 : Normal Mode
01 : Sim Mode
10 : AFE Test Mode
11 : /
24:20
R/W
0x0
PHY_ADDR
PHY Address
19
R/W
0x0
BIST_CLK_EN
0 : BIST clk disable
1 : BIST clk enable
18
R/W
0x1
CLK_SEL
0 : 25MHz
1 : 24MHz
17
R/W
0x0
LED_POL
0 : High active
1 : Low active
16
R/W
0x1
SHUTDOWN
0 : Power up
1 : Shutdown
15
R/W
0x1
PHY_SELECT.
0 : External PHY
1 : Internal PHY
14
/
/
/
13
R/W
0x0
RMII_EN
0 : Disable RMII Module
1 : Enable RMII Module
When this bit assert, MII or RGMII interface is disabled( This means bit13 is
prior to bit2)
12:10
R/W
0x0
ETXDC.
Configure EMAC Transmit Clock Delay Chain.
9:5
R/W
0x0
ERXDC.
Configure EMAC Receive Clock Delay Chain.
4
R/W
0x0
ERXIE
Enable EMAC Receive Clock Invertor.
0: Disable
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