Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 155
4.6. Timer
4.6.1. Overview
Timer 0/1 can take their inputs from Internal OSC or OSC24M. They provide the operating system’s scheduler interrupt.
It is designed to offer maximum accuracy and efficient management, even for systems with long or short response time.
They provide 24-bit programmable overflow counter and work in auto-reload mode or no-reload mode. When the
current value in Current Value Register is counting down to zero, the timer will generate interrupt if set interrupt enable
bit.
The watchdog is used to resume the controller operation when it had been disturbed by malfunctions such as noise and
system errors. It features a down counter that allows a watchdog period of up to 16 seconds (512000 cycles). It can
generate a general reset or interrupt request.
4.6.2. Block Diagram
24M
INOSC/512
Timer 0
Timer 1
Single
Continuous
Interval Value Enable IV=0? Pending
IRQ EN
IRQ
yes
/1
/2
/4
/8
/ 16
/ 32
/ 64
/ 128
Watchdog
Interrupt Enable Pending IRQ
16 k cycles
32 k cycles
64 k cycles
96 k cycles
128 k cycles
160 k cycles
192 k cycles
others cycles
24M/750
Restart
Time out?
yes
Reset
Enable Pending
Restart
Whole System
Reset
yes
Time out?
Figure 4-3. Timer Block Diagram
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