Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 156
4.6.3. Timer Register List
Module Name
Base Address
TIMER
0x01C20C00
Register Name
Offset
Description
TMR_IRQ_EN_REG
0x0
Timer IRQ Enable Register
TMR_IRQ_STA_REG
0x4
Timer Status Register
TMR0_CTRL_REG
0x10
Timer 0 Control Register
TMR0_INTV_VALUE_REG
0x14
Timer 0 Interval Value Register
TMR0_CUR_VALUE_REG
0x18
Timer 0 Current Value Register
TMR1_CTRL_REG
0x20
Timer 1 Control Register
TMR1_INTV_VALUE_REG
0x24
Timer 1 Interval Value Register
TMR1_CUR_VALUE_REG
0x28
Timer 1 Current Value Register
AVS_CNT_CTL_REG
0x80
AVS Control Register
AVS_CNT0_REG
0x84
AVS Counter 0 Register
AVS_CNT1_REG
0x88
AVS Counter 1 Register
AVS_CNT_DIV_REG
0x8C
AVS Divisor Register
WDOG0_IRQ_EN_REG
0xA0
Watchdog 0 IRQ Enable Register
WDOG0_IRQ_STA_REG
0xA4
Watchdog 0 Status Register
WDOG0_CTRL_REG
0xB0
Watchdog 0 Control Register
WDOG0_CFG_REG
0xB4
Watchdog 0 Configuration Register
WDOG0_MODE_REG
0xB8
Watchdog 0 Mode Register
4.6.4. Timer Register Description
4.6.4.1. Timer IRQ Enable Register (Default Value: 0x00000000)
Offset:0x0
Register Name: TMR_IRQ_EN_REG
Bit
R/W
Default/Hex
Description
31:2
/
/
/
1
R/W
0x0
TMR1_IRQ_EN.
Timer 1 Interrupt Enable.
0: No effect;
1: Timer 1 Interval Value reached interrupt enable.
0
R/W
0x0
TMR0_IRQ_EN.
Timer 0 Interrupt Enable.
0: No effect;
1: Timer 0 Interval Value reached interrupt enable.
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