Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 157
4.6.4.2. Timer IRQ Status Register (Default Value: 0x00000000)
Offset:0x04
Register Name: TMR_IRQ_STA_REG
Bit
R/W
Default/Hex
Description
31:2
/
/
/
1
R/W
0x0
TMR1_IRQ_PEND.
Timer 1 IRQ Pending. Set 1 to the bit will clear it.
0: No effect;
1: Pending, timer 1 interval value is reached.
0
R/W
0x0
TMR0_IRQ_PEND.
Timer 0 IRQ Pending. Set 1 to the bit will clear it.
0: No effect;
1: Pending, timer 0 interval value is reached.
4.6.4.3. Timer 0 Control Register (Default Value: 0x00000004)
Offset:0x10
Register Name: TMR0_CTRL_REG
Bit
R/W
Default/Hex
Description
31:8
/
/
/
7
R/W
0x0
TMR0_MODE.
Timer 0 mode.
0: Continuous mode. When interval value reached, the timer will not
disable automatically.
1: Single mode. When interval value reached, the timer will disable
automatically.
6:4
R/W
0x0
TMR0_CLK_PRES.
Select the pre-scale of timer 0 clock source.
000: /1
001: /2
010: /4
011: /8
100: /16
101: /32
110: /64
111: /128
3:2
R/W
0x1
TMR0_CLK_SRC.
Timer 0 Clock Source.
00: Internal OSC / N
01: OSC24M.
10: /
11: /
Internal OSC / N is about 32KHz.
1
R/W
0x0
TMR0_RELOAD.
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