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H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 159
automatically.
1: Single mode. When interval value reached, the timer will disable
automatically.
6:4
R/W
0x0
TMR1_CLK_PRES.
Select the pre-scale of timer 1 clock source.
000: /1
001: /2
010: /4
011: /8
100: /16
101: /32
110: /64
111: /128
3:2
R/W
0x1
TMR1_CLK_SRC.
00: Internal OSC / N
01: OSC24M.
10: /
11: /.
Internal OSC / N is about 32KHz.
1
R/W
0x0
TMR1_RELOAD.
Timer 1 Reload.
0: No effect
1: Reload timer 1 Interval value.
After the bit is set, it can not be written again before it’s cleared
automatically.
0
R/W
0x0
TMR1_EN.
Timer 1 Enable.
0: Stop/Pause
1: Start.
If the timer is started, it will reload the interval value to internal register, and
the current counter will count from interval value to 0.
If the current counter does not reach the zero, the timer enable bit is set to
“0”, the current value counter will pause. At least wait for 2 cycles, the start
bit can be set to 1.
In timer pause state, the interval value register can be modified. If the timer
is started again, and the Software hope the current value register to
down-count from the new interval value, the reload bit and the enable bit
should be set to 1 at the same time.
4.6.4.7. Timer 1 Interval Value Register
Offset:0x24
Register Name: TMR1_INTV_VALUE_REG
Bit
R/W
Default/Hex
Description
31:0
R/W
0x0
TMR1_INTV_VALUE.
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