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H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 161
the internal 33-bits counter register can be set by software. The LSB bit of
the 33-bits counter register should be zero when the initial value is updated.
It will count from the initial value. The initial value can be updated at any
time. It can also be paused by setting AVS_CNT0_PS to ‘1’. When it is paused,
the counter won’t increase.
4.6.4.11. AVS Counter 1 Register (Default Value: 0x00000000)
Offset:0x88
Register Name: AVS_CNT1_REG
Bit
R/W
Default/Hex
Description
31:0
R/W
0x0
AVS_CNT1.
Counter 1 for Audio/ Video Sync Application
The high 32 bits of the internal 33-bits counter register. The initial value of
the internal 33-bits counter register can be set by software. The LSB bit of
the 33-bits counter register should be zero when the initial value is updated.
It will count from the initial value. The initial value can be updated at any
time. It can also be paused by setting AVS_CNT1_PS to ‘1’. When it is paused,
the counter won’t increase.
4.6.4.12. AVS Counter Divisor Register (Default Value: 0x05DB05DB)
Offset:0x8C
Register Name: AVS_CNT_DIV_REG
Bit
R/W
Default/Hex
Description
31:28
/
/
/
27:16
R/W
0x5DB
AVS_CNT1_D.
Divisor N for AVS Counter 1
AVS CN1 CLK=24MHz/Divisor_N1.
Divisor N1 = Bit [27:16] + 1.
The number N is from 1 to 0x7ff. The zero value is reserved.
The internal 33-bits counter engine will maintain another 12-bits counter.
The 12-bits counter is used for counting the cycle number of one 24Mhz
clock. When the 12-bits counter reaches (>= N) the divisor value, the internal
33-bits counter register will increase 1 and the 12-bits counter will reset to
zero and restart again.
Note: It can be configured by software at any time.
15:12
/
/
/
11:0
R/W
0x5DB
AVS_CNT0_D.
Divisor N for AVS Counter 0
AVS CN0 CLK=24MHz/Divisor_N0.
Divisor N0 = Bit [11:0] + 1
The number N is from 1 to 0x7ff. The zero value is reserved.
The internal 33-bits counter engine will maintain another 12-bits counter.
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