Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 162
The 12-bits counter is used for counting the cycle number of one 24Mhz
clock. When the 12-bits counter reaches (>= N) the divisor value, the internal
33-bits counter register will increase 1 and the 12-bits counter will reset to
zero and restart again.
Note: It can be configured by software at any time.
4.6.4.13. Watchdog0 IRQ Enable Register (Default Value: 0x00000000)
Offset:0xA0
Register Name: WDOG0_IRQ_EN_REG
Bit
R/W
Default/Hex
Description
31:1
/
/
/
0
R/W
0x0
WDOG0_IRQ_EN.
Watchdog0 Interrupt Enable.
0: No effect
1: Watchdog0 interrupt enable.
4.6.4.14. Watchdog0 Status Register (Default Value: 0x00000000)
Offset:0xA4
Register Name: WDOG0_IRQ_STA_REG
Bit
R/W
Default/Hex
Description
31:1
/
/
/
0
R/W
0x0
WDOG0_IRQ _PEND.
Watchdog0 n IRQ Pending. Set 1 to the bit will clear it.
0: No effect,
1: Pending, watchdog0 interval value is reached.
4.6.4.15. Watchdog0 Control Register (Default Value: 0x00000000)
Offset:0xB0
Register Name: WDOG0_CTRL_REG
Bit
R/W
Default/Hex
Description
31:13
/
/
/
12:1
R/W
0x0
WDOG0_KEY_FIELD.
Watchdog0 Key Field.
Should be written at value 0xA57. Writing any other value in this field aborts
the write operation.
0
R/W
0x0
WDOG0_RSTART.
Watchdog0 Restart.
0: No effect,
1: Restart watchdog0.
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