Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 167
4.7.5. TWD Register Description
4.7.5.1. TWD Status Register (Default Value: 0x00000000)
Offset: 0x0000
Register Name: TWD_STATUS_REG
Bit
R/W
Default/Hex
Description
31:1
/
/
/
0
R/W
0x0
TWD_PEND_FLAG.
Interrupt pending. Set 1 to the bit will clear it.
0: No effect.
1: Pending.
4.7.5.2. TWD Control Register (Default Value: 0x00000000)
Offset: 0x0010
Register Name: TWD_CTRL_REG
Bit
R/W
Default/Hex
Description
31
R/W
0x0
CNT64_CLK_SRC_SEL.
64-bit counter clock source select.
0: LOSC.
1: OSC24M.
30:10
/
/
/
9
R/W
0x0
TWD_RESET_EN.
TWD reset enable.
0: Reset disable.
1: Reset enable.
8
R/W
0x0
TWD_INT_EN.
TWD Interrupt Enable.
0: Interrupt disable.
1: Interrupt enable.
7:2
/
/
/
1
R/W
0x0
TWD_STOP_EN.
TWD stop enable.
0: Resume rolling-over.
1: Stop rolling-over.
0
R/W
0x0
TWD_CLR_EN.
TWD clear enable.
0: No effect.
1: To clear relevant registers and it will change to zero after the registers are
cleared.
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