Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 176
Alarm 0 IRQ Enable.
0: Disable
1: Enable
4.8.3.10. Alarm 0 IRQ Status Register (Default Value: 0x00000000)
Offset:0x30
Register Name: ALARM0_IRQ_STA_REG
Bit
R/W
Default/Hex
Description
31:1
/
/
/
0
R/W
0x0
ALARM0_IRQ_PEND.
Alarm 0 IRQ Pending bit.
0: No effect
1: Pending, alarm 0 counter value is reached
If alarm 0 irq enable is set to 1, the pending bit will be sent to the interrupt
controller.
4.8.3.11. Alarm 1 Week HH-MM-SS Register (Default Value: 0x00000000)
Offset:0x40
Register Name: ALARM1_WK_HH_MM-SS
Bit
R/W
Default/Hex
Description
31:21
/
/
/
20:16
R/W
x
HOUR.
Range from 0~23.
15:14
/
/
/
13:8
R/W
x
MINUTE.
Range from 0~59.
7:6
/
/
/
5:0
R/W
x
SECOND.
Range from 0~59.
Note: If the written value is not from 0 to 59 in Second Area, it turns into 59 automatically. Minute Area and Hour Area
are similar to Second Area.
4.8.3.12. Alarm 1 Enable Register (Default Value: 0x00000000)
Offset:0x44
Register Name: ALARM1_EN_REG
Bit
R/W
Default/Hex
Description
31:7
/
/
/
6
R/W
0x0
WK6_ALM1_EN.
Week 6 (Sunday) Alarm 1 Enable.
0: Disable
confidential