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H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 177
1: Enable
If this bit is set to “1”, only when the Alarm 1 Week HH-MM-SS register valid
bits is equal to RTC HH-MM-SS register and the register RTC HH-MM-SS bit
[31:29] is 6, the week 6 alarm irq pending bit will be set to “1”.
5
R/W
0x0
WK5_ALM1_EN.
Week 5 (Saturday) Alarm 1 Enable.
0: Disable
1: Enable
If this bit is set to “1”, only when the Alarm 1 Week HH-MM-SS register valid
bits is equal to RTC HH-MM-SS register and the register RTC HH-MM-SS bit
[31:29] is 5, the week 5 alarm irq pending bit will be set to “1”.
4
R/W
0x0
WK4_ALM1_EN.
Week 4 (Friday) Alarm 1 Enable.
0: Disable
1: Enable
If this bit is set to “1”, only when the Alarm 1 Week HH-MM-SS register valid
bits is equal to RTC HH-MM-SS register and the register RTC HH-MM-SS bit
[31:29] is 4, the week 4 alarm irq pending bit will be set to “1”.
3
R/W
0x0
WK3_ALM1_EN.
Week 3 (Thursday) Alarm 1 Enable.
0: Disable
1: Enable
If this bit is set to “1”, only when the Alarm 1 Week HH-MM-SS register valid
bits is equal to RTC HH-MM-SS register and the register RTC HH-MM-SS bit
[31:29] is 3, the week 3 alarm irq pending bit will be set to “1”.
2
R/W
0x0
WK2_ALM1_EN.
Week 2 (Wednesday) Alarm 1 Enable.
0: Disable
1: Enable
If this bit is set to “1”, only when the Alarm 1 Week HH-MM-SS register valid
bits is equal to RTC HH-MM-SS register and the register RTC HH-MM-SS bit
[31:29] is 2, the week 2 alarm irq pending bit will be set to “1”.
1
R/W
0x0
WK1_ALM1_EN.
Week 1 (Tuesday) Alarm 1 Enable.
0: Disable
1: Enable
If this bit is set to “1”, only when the Alarm 1 Week HH-MM-SS register valid
bits is equal to RTC HH-MM-SS register and the register RTC HH-MM-SS bit
[31:29] is 1, the week 1 alarm irq pending bit will be set to “1”.
0
R/W
0x0
WK0_ALM1_EN.
Week 0 (Monday) Alarm 1 Enable.
0: Disable
1: Enable
If this bit is set to “1”, only when the Alarm 1 Week HH-MM-SS register valid
bits is equal to RTC HH-MM-SS register and the register RTC HH-MM-SS bit
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