Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 178
[31:29] is 0, the week 0 alarm irq pending bit will be set to “1”.
4.8.3.13. Alarm 1 IRQ Enable Register (Default Value: 0x00000000)
Offset:0x48
Register Name: ALARM1_IRQ_EN
Bit
R/W
Default/Hex
Description
31:1
/
/
/
0
R/W
0x0
ALARM1_IRQ_EN.
Alarm 1 IRQ Enable.
0: Disable
1: Enable
4.8.3.14. Alarm 1 IRQ Status Register (Default Value: 0x00000000)
Offset:0x4C
Register Name: ALARM1_IRQ_STA_REG
Bit
R/W
Default/Hex
Description
31:1
/
/
/
0
R/W
0x0
ALARM1_WEEK_IRQ_PEND.
Alarm 1 Week (0/1/2/3/4/5/6) IRQ Pending.
0: No effect
1: Pending, week counter value is reached
If alarm 1 week irq enable is set to 1, the pending bit will be sent to the
interrupt controller.
4.8.3.15. Alarm Config Register (Default Value: 0x00000000)
Offset:0x50
Register Name: ALARM_CONFIG_REG
Bit
R/W
Default/Hex
Description
31:1
/
/
/
0
R/W
0x0
ALARM_WAKEUP.
Configuration of alarm wake up output.
0: Disable alarm wake up output
1: Enable alarm wake up output
4.8.3.16. LOSC Output Gating Register (Default Value: 0x00000000)
Offset:0x60
Register Name: LOSC_OUT_GATING_REG
Bit
R/W
Default/Hex
Description
31:1
/
/
/
confidential