Owners manual

H3
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 18
4.15.2.1. Block Diagram ......................................................................................................................... 227
4.15.2.2. Crypto Engine Task Descriptor................................................................................................. 227
4.15.3. Crypto Engine Register List ................................................................................................................ 230
4.15.4. Crypto Engine Register Description ................................................................................................... 230
4.15.4.1. Crypto Engine Task Descriptor Queue Register(Default Value: 0x00000000) ......................... 230
4.15.4.2. Crypto Engine Control Register ............................................................................................... 231
4.15.4.3. Crypto Engine Interrupt Control Register(Default Value: 0x00000000).................................. 231
4.15.4.4. Crypto Engine Interrupt Status Register(Default Value: 0x00000000).................................... 231
4.15.4.5. Crypto Engine Task Load Register(Default Value: 0x00000000) ............................................. 231
4.15.4.6. Crypto Engine Error Status Register(Default Value: 0x00000000) .......................................... 232
4.15.4.7. Crypto Engine Current Source Scatter Group Register(Default Value: 0x00000000) .............. 232
4.15.4.8. Crypto Engine Current Destination Scatter Group Register(Default Value: 0x00000000) ...... 232
4.15.4.9. Crypto Engine Current Source Address Register(Default Value: 0x00000000) ....................... 233
4.15.4.10. Crypto Engine Current Destination Address Register(Default Value: 0x00000000).............. 233
4.15.4.11. Crypto Engine Throughput Register(Default Value: 0x00000000) ........................................ 233
4.15.5. Crypto Engine Clock Requirement ..................................................................................................... 233
4.15.6. Programming Guidelines ................................................................................................................... 233
4.16. Security ID ................................................................................................................................................. 236
4.16.1. Overview ........................................................................................................................................... 236
4.17. Secure Memory Controller ........................................................................................................................ 237
4.17.1. Overview ........................................................................................................................................... 237
4.17.2. Functionalities Description ................................................................................................................ 237
4.17.2.1. DRM Block Diagram ................................................................................................................ 238
4.17.2.2. Master ID Table ....................................................................................................................... 238
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