Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 181
Hold the output of GPIOL2 when system’s power is changing. The output
must be low level (0) or high level (1) or High-Z; any other outputs may not
hold on.
0: Hold disable
1: Hold enable
1
R/W
0x0
GPL1_HOLD_OUTPUT.
Hold the output of GPIOL1 when system’s power is changing. The output
must be low level (0) or high level (1) or High-Z; any other outputs may not
hold on.
0: Hold disable
1: Hold enable
0
R/W
0x0
GPL0_HOLD_OUTPUT.
Hold the output of GPIOL0 when system’s power is changing. The output
must be low level (0) or high level (1) or High-Z; any other outputs may not
hold on.
0: Hold disable
1: Hold enable
4.8.3.20. VDD RTC Regulation Register (Default Value: 0x00000004)
Offset:0x190
Register Name: VDD_RTC_REG
Bit
R/W
Default/Hex
Description
31:3
/
/
/
2:0
R/W
0x100
VDD_RTC_REGU.
These bits are useful for regulating the RTC_VIO from 0.7v to 1.4v, and the
regulation step is 0.1v.
000: 0.7v
001: 0.8v
010: 0.9v
011: 1.0v
100: 1.1v
101: 1.2v
110: 1.3v
111: 1.4v
4.8.3.21. IC Characteristic Register (Default Value: 0x00000000)
Offset:0x1F0
Register Name: IC_CHARA_REG
Bit
Read/Write
Default/Hex
Description
31:16
R/W
0x0
IC_CHARA.
Key Field.
Should be written at value 0x16AA. Writing any other value in this field
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