Owners manual

System

4.9. High-speed Timer

4.9.1. Overview

High Speed Timer Clock Source are fixed to AHBCLK, which is much higher than OSC24M. Compared with other timers,

High Speed Timer clock source is synchronized with AHB clock, and when the relevant bit in the Control Register is set 1,

timer goes into the test mode, which is used to System Simulation. When the current value in both LO and HI Current

Value Register are counting down to zero, the timer will generate interrupt if set interrupt enable bit.

The High Speed Timer includes the following features:

 56-bit counter

 Clock source is synchronized with AHB clock, which means calculating much more accurate than other timers

4.9.2. Operation Principle

4.9.2.1. HSTimer clock gating and software reset

By default the HSTimer clock gating is mask. When it is necessary to use HSTimer, it’s clock gating should be open in

BUS Clock Gating Register0 and then de-assert the software reset in BUS Software Reset Register0 on CCU module. If it

is no need to use HSTimer, both the gating bit and software reset bit should be set 0.

4.9.2.2. HSTimer reload bit

Differing from the reload of Timer, when interval value is reloaded into current value register, the reload bit would not

turn to 0 automatically until you clear it. If software hopes the current value register to down-count from the new

interval value in pause status, the reload bit and the enable bit should be written 1 at the same time.

4.9.3. HSTimer Register List

Module Name

Base Address

High Speed Timer

0x01C60000

Offset

Description

HS_TMR_IRQ_EN_REG

0x00

HS Timer IRQ Enable Register

HS_TMR_IRQ_STAS_REG

0x04

HS Timer Status Register

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