Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 184
HS_TMR_CTRL_REG
0x10
HS Timer Control Register
HS_TMR_INTV_LO_REG
0x14
HS Timer Interval Value Low Register
HS_TMR_INTV_HI_REG
0x18
HS Timer Interval Value High Register
HS_TMR_CURNT_LO_REG
0x1C
HS Timer Current Value Low Register
HS_TMR_CURNT_HI_REG
0x20
HS Timer Current Value High Register
4.9.4. HSTimer Register Description
4.9.4.1. HS Timer IRQ Enable Register (Default Value: 0x00000000)
Offset:0x0
Register Name: HS_TMR_IRQ_EN_REG
Bit
R/W
Default/Hex
Description
31:1
/
/
/
0
R/W
0x0
HS_TMR_INT_EN.
High Speed Timer Interrupt Enable.
0: No effect;
1: High Speed Timer Interval Value reached interrupt enable.
4.9.4.2. HS Timer IRQ Status Register (Default Value: 0x00000000)
Offset:0x4
Register Name: HS_TMR_IRQ_STAS_REG
Bit
R/W
Default/Hex
Description
31:1
/
/
/
0
R/W
0x0
HS_TMR_IRQ_PEND.
High Speed Timer IRQ Pending. Set 1 to the bit will clear it.
0: No effect;
1: Pending, High speed timer interval value is reached.
4.9.4.3. HS Timer Control Register (Default Value: 0x00000000)
Offset:0x10
Register Name: HS_TMR_CTRL_REG
Bit
R/W
Default/Hex
Description
31
R/W
0x0
HS_TMR_TEST.
High speed timer test mode. In test mode, the low register should be set to
0x1, the high register will down counter. The counter needs to be reloaded.
0: normal mode;
1: test mode.
30:8
/
/
/
7
R/W
0x0
HS_TMR_MODE.
High Speed Timer mode.
0: Continuous mode. When interval value reached, the timer will not disable
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