Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 185
automatically.
1: Single mode. When interval value reached, the timer will disable
automatically.
6:4
R/W
0x0
HS_TMR_CLK
Select the pre-scale of the high speed timer clock sources.
000: /1
001: /2
010: /4
011: /8
100: /16
101: /
110: /
111: /
3:2
/
/
/
1
R/W
0x0
HS_TMR_RELOAD.
High Speed Timer Reload.
0: No effect, 1: Reload High Speed Timer Interval Value.
0
R/W
0x0
HS_TMR_EN.
High Speed Timer Enable.
0: Stop/Pause, 1: Start.
If the timer is started, it will reload the interval value to internal register, and
the current counter will count from interval value to 0.
If the current counter does not reach the zero, the timer enable bit is set to
“0”, the current value counter will pause. At least wait for 2 cycles, the start
bit can be set to 1.
In timer pause state, the interval value register can be modified. If the timer
is started again, and the Software hope the current value register to
down-count from the new interval value, the reload bit and the enable bit
should be set to 1 at the same time.
4.9.4.4. HS Timer Interval Value Lo Register
Offset:0x14
Register Name: HS_TMR_INTV_LO_REG
Bit
R/W
Default/Hex
Description
31:0
R/W
x
HS_TMR_INTV_VALUE_LO.
High Speed Timer Interval Value [31:0].
4.9.4.5. HS Timer Interval Value Hi Register
Offset:0x18
Register Name: HS_TMR_INTV_HI_REG
Bit
R/W
Default/Hex
Description
31:24
/
/
/
23:0
R/W
x
HS_TMR_INTV_VALUE_HI.
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