Owners manual

System

4.10. PWM

4.10.1. Overview

The output of the PWM is a toggling signal whose frequency and duty cycle can be modulated by its programmable

registers. Each channel has a dedicated internal 16-bit up counter. If the counter reaches the value stored in the channel

period register, it resets. At the beginning of a count period cycle, the PWMOUT is set to active state and count from

0x0000.The PWM divider divides the clock(24MHz) by 1~4096 according to the pre-scalar bits in the PWM control

In PWM cycle mode, the output will be a square waveform, the frequency is set to the period register. In PWM pulse

mode, the output will be a positive pulse or a negative pulse.

4.10.2. PWM Block Diagram

Cycle Mode

Entire cycles

Active low

Active cycles

Pulse Mode

Active high

Active cycles

Figure 4-5. PWM Block Diagram

When PWM is enabling, the PWM can output two signals, which are reversed on two pins. And when PWM is disabling,

the PWM can control the status of two pins. The PWM divider divides the clock (24MHz) by 1-64 according to the

pre-scalar bits in the PWM control register. The PWM output Frequency can be divided by 65536 at most. In PWM cycle

mode, the output will be a square waveform; the frequency is set to the period register. In PWM pulse mode, the

output will be a positive pulse or a negative pulse.

4.10.3. PWM Register List

Module Name

Base Address

PWM

0x01C21400

Offset

Description

PWM_CH_CTRL

0x00

PWM Control Register

PWM_CH0_PERIOD

0x04

PWM Channel 0 Period Register

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