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System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 188
4.10.4. PWM Register Description
4.10.4.1. PWM Control Register(Default Value: 0x00000000)
Offset:0x0
Register Name: PWM_CTRL_REG
Bit
R/W
Default/Hex
Description
31:29
/
/
/.
28
RO
0x0
PWM0_RDY.
PWM0 period register ready.
0: PWM0 period register is ready to write,
1: PWM0 period register is busy.
27:10
/
/
/
9
R/W
0x0
PWM0_BYPASS.
PWM CH0 bypass enable.
If the bit is set to 1, PWM0’s output is OSC24MHz.
0: disable,
1: enable.
8
R/W
0x0
PWM_CH0_PUL_START.
PWM Channel 0 pulse output start.
0: no effect,
1: output 1 pulse.
The pulse width should be according to the period 0 register[15:0],and the
pulse state should be according to the active state.
After the pulse is finished,the bit will be cleared automatically.
7
R/W
0x0
PWM_CHANNEL0_MODE.
0: cycle mode,
1: pulse mode.
6
R/W
0x0
SCLK_CH0_GATING.
Gating the Special Clock for PWM0(0: mask, 1: pass).
5
R/W
0x0
PWM_CH0_ACT_STA.
PWM Channel 0 Active State.
0: Low Level,
1: High Level.
4
R/W
0x0
PWM_CH0_EN.
PWM Channel 0 Enable.
0: Disable,
1: Enable.
3:0
R/W
0x0
PWM_CH0_PRESCAL.
PWM Channel 0 Prescalar.
These bits should be setting before the PWM Channel 0 clock gate on.
0000: /120
0001: /180
0010: /240
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