Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 189
0011: /360
0100: /480
0101: /
0110: /
0111: /
1000: /12k
1001: /24k
1010: /36k
1011: /48k
1100: /72k
1101: /
1110: /
1111: /1
4.10.4.2. PWM Channel 0 Period Register(Default Value: 0x00000000)
Offset:0x4
Register Name: PWM_CH0_PERIOD
Bit
R/W
Default/Hex
Description
31:16
R/W
x
PWM_CH0_ENTIRE_CYS
Number of the entire cycles in the PWM clock.
0 = 1 cycle
1 = 2 cycles
……
N = N+1 cycles
If the register need to be modified dynamically, the PCLK should be faster
than the PWM CLK (PWM CLK = 24MHz/pre-scale).
15:0
R/W
x
PWM_CH0_ENTIRE_ACT_CYS
Number of the active cycles in the PWM clock.
0 = 0 cycle
1 = 1 cycles
……
N = N cycles
Note:The active cycles should be no larger than the period cycles.
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