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System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 190
4.11. DMA
4.11.1. Overview
There are 12 DMA channels in the chip. Each DMA channel can generate interrupts. According to different pending
status, the referenced DMA channel generates corresponding interrupt. And, the configuration information of every
DMA channel are storing in the DDR or SRAM. When start a DMA transferring, the DMA Channel Descriptor Address
Register contains the address information in the DDR or SRAM, where has the relevance configuration information of
the DMA transferring.
4.11.2. Functionalities Description
4.11.2.1. Block Diagram
Source
Address
Configuration
Destination
Address
Byte Counter
Link
Descriptor information
Pending Status
Pkg-pend
End-pend
Commity
Parameter
Half-pend
Request DMA
Any
Idle?
Write Descriptor
Address and Start DMA
Transferring Package
Pause?
Link=fffff 800?
DMA Transfer Progress
Prepare Descriptor Data
1
Link
2
Link
3
Link
4
0xfffff 800
Pkg-pend
Half-pend
Pkg-pend
Half-pend
Pkf-pend
Half-pend
After transferring a half data of a pkg, the pkg half pending bit would set up
After transferring all data of pkg, the pkg end pending bit would set up
After finishing a transmission, the queue end pending bit would set up
Link is used to storing next descriptor address or transmission end flag (0xfffff800)
Pkg-pend
Half-pend
Yes
Resume
No
No
End-pend
Transmission Finish
DMA
DMAC obtains
Descriptor information
Figure 4-6. DMA Block Diagram
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