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H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 191
4.11.2.2. DRQ Type and Corresponding Relation
Table 4-1. DMA DRQ Table
Source DRQ Type
Destination DRQ Type
Port NO.
Module Name
Port NO.
Module Name
Port 0
SRAM
Port 0
SRAM
Port 1
SDRAM
Port 1
SDRAM
Port 2
/
Port 2
OWA_TX
Port 3
I2S/PCM 0_RX
Port 3
I2S/PCM 0_TX
Port 4
I2S/PCM 1_RX
Port 4
I2S/PCM 1_TX
Port 5
NAND
Port 5
NAND
Port 6
UART0_RX
Port 6
UART0_TX
Port 7
UART1_RX
Port 7
UART1_TX
Port 8
UART2_RX
Port 8
UART2_TX
Port 9
UART3_RX
Port 9
UART3_TX
Port 10
/
Port 10
/
Port 11
/
Port 11
/
Port 12
/
Port 12
/
Port 13
/
Port 13
/
Port 14
/
Port 14
/
Port 15
Audio Codec
Port 15
Audio Codec
Port 16
/
Port 16
/
Port 17
USB OTG_Device_EP1
Port 17
USB OTG_Device_EP1
Port 18
USB OTG_Device_EP2
Port 18
USB OTG_Device_EP2
Port 19
USB OTG_Device_EP3
Port 19
USB OTG_Device_EP3
Port20
USB OTG_Device_EP4
Port 20
USB OTG_Device_EP4
Port 21
/
Port 21
/
Port 22
/
Port 22
/
Port 23
SPI0_RX
Port 23
SPI0_TX
Port 24
SPI1_RX
Port 24
SPI1_TX
Port 25
Port 25
Port 26
Port 26
Port 27
Port 27
I2S/PCM 2_TX
Port 28
Port 28
Port 29
Port 29
Port 30
Port 30
Note:SRAM or DRAM DRQ signal is always high.
4.11.2.3. DMA Descriptor
In this section, the DMA descriptor registers will be introduced in detail.
When starting a DMA transmission, the module data are transferred as packages, which have the link data information.
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