Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 192
And, by reading the DMA Status Register, the status of a DMA channel could be known. Reading back the descriptor
address register, the value is the link data in the transferring package. If only the value is equal to 0xfffff800, then it can
be regarded as NULL, which means the package is the last package in this DMA transmission. Otherwise, the value
means the start address of the next package. And, the Descriptor Address Register can be changed during a package
transferring.
When transferring the half of a package, the relevant pending bit will be set up automatically, and if the corresponding
interrupt is enabled, DMA generates an interrupt to the system. The similar thing would occur when transferring a
package completely. Meanwhile, if DMA have transferred the last package in the data, the relevant pending bit would
be set up, and generates an interrupt if the corresponding interrupt is enabled. The flow-process diagram is showed in
Block Diagram section.
During a DMA transmission, the configuration could be obtained via the Configuration Register. And, behind the address
of the config register in DDR or SRAM, there are some registers including other information of a DMA transmission. The
structure chart is showed in Block Diagram section. Also, other information of a transferring data can be obtained by
reading the Current Source Address Register, Current Destination Address Register and Byte Counter Left Register. The
configuration must be word-aligning.
The transferring data would be paused when setting up the relevant Pause Register, if coming up emergency. And the
pausing data could be presumable when set 0 to the same bit in Pause Register.
4.11.3. DMA Register List
Module Name
Base Address
DMA
0x01C02000
Register Name
Offset
Description
DMA_IRQ_EN_REG0
0x00
DMA IRQ Enable Register0
DMA_IRQ_EN_REG1
0x04
DMA IRQ Enable Register1
DMA_IRQ_PEND_REG0
0x10
DMA IRQ Pending Register0
DMA_IRQ_PEND_REG1
0x14
DMA IRQ Pending Register1
DMA_SEC_REG
0x20
DMA Security Register
DMA_AUTO_GATE_REG
0x28
DMA Auto Gating Register
DMA_STA_REG
0x30
DMA Status Register
DMA_EN_REG
0x100+N*0x40
DMA Channel Enable Register
(N=0~11)
DMA_PAU_REG
0x100+N*0x40+0x4
DMA Channel Pause Register
(N=0~11)
DMA_DESC_ADDR_REG
0x100+N*0x40+0x8
DMA Channel Start Address Register
(N=0~11)
DMA_CFG_REG
0x100+N*0x40+0xC
DMA Channel Configuration Register
(N=0~11)
DMA_CUR_SRC_REG
0x100+N*0x40+0x10
DMA Channel Current Source Register
(N=0~11)
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